Abstract
A REVIEW ON DESIGN AND IMPLEMENTATION OF 6T SRAM USING FINFET WITH LOW POWER APPLICATION
Jigyasa Panchal* and Dr. Vishal Ramola
ABSTRACT
CMOS devices are facing many problems because the gate starts losing control over the channel. These problems includes increase in leakage currents, increase of on current, increase in manufacturing cost, large variations in parameters, less reliability and yield, short channel effects etc. In the past few years we have come through a new technology known as FINFET. FINFET is a multi gate device which is used to over come all these problems which are now being faced by CMOS technology especially short channel effects. Since conventional CMOS is used to design SRAM, but it is also facing the problem of high power dissipation and increase in leakage current which affects its performance badly. Memories are required to have short access time, less power dissipation and low leakage current thus FINFET based SRAM cells are recommended over CMOS based SRAM cells. FINFET based SRAM cells are more popular due to the low power dissipation. FINFET based 6T SRAM cell structure differs from the conventional 6T SRAM. Reducing the leakage aspects of the SRAM cells has been very essential to enhance the stability of the cell. Therefore many low power techniques are used to reduce the power dissipation and leakage currents. These include Multithreshold CMOS (MTCMOS), variable threshold CMOS (VTCMOS), Stacking technique, power gating, Self controllable voltage level (SVL) technique etc.
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