Abstract
DESIGN AND VERIFICATION OF PRIORITY CONFIGURABLE INTERRUPT CONTROLLER
Mukthi. S. L* and Dr. A. R. Aswatha
ABSTRACT
Interrupt helps in communicating the processors and peripherals. But number of interrupt ports on processor are far less compared to interrupt signals from other processor and peripherals in a system on chip (SOC) design. This creates an serious issue in the multi-processor SOC design also. Interrupt Controller is the key solution to above problem. The function of Interrupt Controller is to sort the interrupt signals from peripherals and processor based on priority level and put forward the interrupt which has got highest priority for processing. The priority level assignment can be configured. In this proposed design, priority level is configured by software. The proposed design is also combining interrupts and then assert the interrupts to the processor. Our design can handle up to 60 interrupt signals from various peripherals and produces the 12 output signals. The AMBA AHB act as bus interface between processor and Interrupt Controller Formal verifications of the proposed Interrupt controller has been done.
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