Abstract
DESIGN AND PARAMETRIC ANALYSIS OF DUAL WORK FUNCTION PILE GATE APPROACH FOR LOW LEAKAGE FINFET
Udit Shah* and Amit Kumar
ABSTRACT
According to Moore's law scaling of CMOS technologies beyond 22nm is limited by factors like excessive power consumption, process variation effects and other short channel effects (SCEs) like Drain Induce Barrier Lowering (DIBL), Gate Induce Drain Leakage (GIDL) and Vth roll off. Double Gate MOSFETs (DG MOSFET) is one of the solution to these SCEs but due to fabrication difficulties like misalignment of top and bottom gates etc. DG MOSFETs are replaced by FinFET. FinFET (Fin Field-Effect Transistor) innovation has as if now observed a noticeable increment in the selection of inbuilt circuits due to its high sensitivity to short channel impacts and its further strength to scale it down. Already, a noticeable research work was made to reduce the leakage current in the standard bulk devices. Such a large number of various choices like mass separation and oxide confinement are all having a few pros and cons. Here in this work, a novel Pile gate FinFET structure is introduced to overcome the short channel effects, unlike from Bulk FinFET without utilizing any pstop implant or isolation oxide as in the Silicon-on-Insulator (SOI). The real favorable position of this kind of structure is that there is no need of high substrate doping, a 100% decrement in the random dopant fluctuation (RDF) and an expansion in the ION/IOFF esteem. It can be exceptionally valuable to enhance the drain-induced barrier lowering (DIBL) at smaller tech. For the simulation of modelled and designed structure Cogenda Visual TCAD 1.8.0.4 tool has been used.
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