Abstract
LOW-VOLTAGE RADIATION-HARDENED SRAM
Sindhu S. J.* and Mukthi S.L.
ABSTRACT
The VLSI circuits are prone to soft errors when they are exposed to extreme environmental conditions and there is a growing demand for low-voltage, low-power applications. The memory arrays consist of very crucial data and take enormous areas on the silicon dies. Radiation Hardening can be achieved by implementing large arrays or redundant bitcells and operated on high voltage, this adds to the overhead of area and limits the minimum operating voltage. This paper proposes high soft-error robust, low-voltage and radiation-hardened Static Random Access Memory. The proposed cell layout is only two times larger than the conventional 6T SRAM. The 13T SRAM proposed has a dual-driven separated-feedback mechanism which can tolerate high charge deposits and has low Supply Voltage. 0.45micrometer CMOS technology is used in designing the 32*32 array with a low subthreshold voltage.
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