Abstract
A LOW POWER HIGH SPEED 32/33 PRESCALER BASED ON DIVIDE BY 2/3 WITH TRUE SINGLE PHASE CLOCK LOGIC
Neetu Sharma* and Uma Nirmal
ABSTRACT
A low-power high-speed based on divide-by-2/3 divider, dual modulus divide by 32/33 prescaler is designed with characteristics of low supply voltage, high operating frequency and low-power consumption. The design uses TSPC logic to decrease the power consumption and increase the noise performance. The circuit is simulated at 180 nm low power CMOS process. The simulated results show that the highest operating frequency is up to 28.57 GHz and running at a power supply of 1v, the circuit consumes only 1.01 ?W at input frequency.
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