Abstract
A NOVEL FPGA BASED MAC UNIT DESIGN USING REVERSIBLE LOGIC GATE APPROACH
M. Sirisha*, Dr. K. V. Rama Rao and B. Venkateswara Rao
ABSTRACT
In this paper, a design of Multiply and Accumulate (MAC) unit using reversible logic gates is proposed. This methodology enables us to design high-performance low power, Very Large Scale Integration [VLSI] systems for different real-time applications. In this work, a 4- bit MAC unit is designed with Sirisha-Purushottam-Tilak (SPT) reversible gate. The 4-bit MAC unit is modeled using Verilog and implemented on the SPARTAN 3E family on the XC3S500E using Xilinx 14.7 (IDE). The performance has been evaluated using parameters such as gate count, garbage outputs, propagation delay, and power dissipation. The performance of the proposed system found to be superior compared to the MAC unit designed with Toffoli, Fredkin, and Feynman gates.
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