Abstract
IMPLEMENTATION OF GLITCH-FREE DIGITALLY CONTROLLED DELAY LINES
Priya Bahguna* and Dr. Vishal Ramola
ABSTRACT
The recently proposed NAND-based digitally controlled delay-lines (DCDL) present a glitching problem which may limit their employ in many applications. This paper presents a glitch-free NAND-based DCDL which overcame this limitation by opening the employ of NAND-based DCDLs in a wide range of applications. The basic aim is to find out a glitch free digitally controlled delay lines with minimum power consumption and minimum area requirement. Here we are using a NAND based digitally controlled delay lines to make the circuit glitch free.
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